1. Field of the Invention
The present invention relates to a data processing technique for realizing suitable parallel processing by controlling data flow in a plurality of data processing modules connected to a plurality of ring buses.
2. Description of the Related Art
Conventionally, to execute a series of data processing efficiently at high speed, the series of data processing is divided, and allocated to hardware modules. In this way, by connecting the hardware modules with each other in the order of the processing, pipeline processing is executed at high speed.
Further, in some cases of image processing, by changing the order of the processing executed by hardware modules, the processing can be executed efficiently. For example, when a processed image is output to an output apparatus configured to handle a predetermined pixel number, resolution conversion for adjusting the pixel number (or resolution) needs to be executed somewhere in a series of processing. In this case, when the pixel number of the input image is greater than the pixel number that can be handled by the output apparatus, the resolution conversion is executed in upstream-side processing, since it is preferable that the image is processed after the pixel number is reduced. On the other hand, when the pixel number of the input image is less than the pixel number that can be handled by the output apparatus, it is preferable that the image is processed while maintaining the small number of pixels without executing the resolution conversion and the resolution conversion is executed on the image immediately before output, namely, in downstream-side processing.
It is assumed data is converted from one space (e.g. a space of an input device) into a standard space (e.g. resolution 600 pixel per inch (ppi), and CIELAB color space) to be processed and the processed data is further converted from the standard space into another space (e.g. a space of an output device). In this case, the order of the processing executed by space conversion units on input and output sides (the order of the processing concerning a one-dimensional look-up table (LUT), matrix calculation, three-dimensional LUT, and the like) is reversed. In other words, if the order of the processing can be changed, the same processing module can be shared on the input and output sides.
However, based on the above conventional method of connecting hardware modules with each other in the order of the processing, the order of the processing executed by the modules cannot be changed. Thus, to accommodate the above case, additional modules (namely, a plurality of modules having the same function) need to be mounted.
According to a method discussed in Japanese Patent Application Laid-Open No. 01-023340, by changing a data connection destination in a ring network, the order of the processing executed by the modules can be changed, and therefore, the above additional modules can be eliminated. Further, contents of the processing executed by each processing module can be changed, as discussed in Japanese Patent No. 2518293.
Japanese Patent No. 2834210 discusses a data flow control method for improving extendability and maintainability by using broadcast communication.
However, according to the conventional methods, it is difficult to control complex data flows, such as data flow branches (reference to identical data by a plurality of modules), simultaneous execution of a plurality of data flows, and time-division multiplexing by processing modules. Data flow branches (reference to identical data by a plurality of modules) can be realized by using broadcast communication as discussed in Japanese Patent No. 2834210. However, data flow control for realizing data flow integration, simultaneous execution of a plurality of data flows, time-division multiplexing by processing modules, and the like is complex, and the transfer efficiency may be decreased.